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Data Sheet
ADE7758
INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A)
The interrupt status register is used to determine the source of a n interrupt event. When an interrupt event occurs in the ADE7758 , the
corresponding flag in the interrupt status register is set. The IRQ pin goes active low if the corresponding bit in the interrupt mask
register is set. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the
source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after an event occurs. The state of the
interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read.
Table 24. Interrupt Status Register
Bit
Interrupt
Default
Location
0
Flag
AEHF
Value
0
Event Description
Indicates that an interrupt was caused by a change in Bit 14 among any one of the three WATTHR
registers, that is, the WATTHR register is half full.
1
REHF
0
Indicates that an interrupt was caused by a change in Bit 14 among any one of the three VARHR
registers, that is, the VARHR register is half full.
2
VAEHF
0
Indicates that an interrupt was caused by a 0 to 1 transition in Bit 15 among any one of the three VAHR
registers, that is, the VAHR register is half full.
3
4
5
6
7
8
9
10
11
12
SAGA
SAGB
SAGC
ZXTOA
ZXTOB
ZXTOC
ZXA
ZXB
ZXC
LENERGY
0
0
0
0
0
0
0
0
0
0
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A.
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B.
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C.
Indicates a detection of a rising edge zero crossing in the voltage channel of Phase A.
Indicates a detection of a rising edge zero crossing in the voltage channel of Phase B.
Indicates a detection of a rising edge zero crossing in the voltage channel of Phase C.
In line energy accumulation, indicates the end of an integration over an integer number of half-line
cycles (LINECYC). See the Calibration section.
13
Reset
1
After Bit 6 (SWRST) in OPMODE register is set to 1, the ADE7758 enters software reset. This bit
becomes 1 after 166 μsec, indicating the reset process has ended and the registers are set to their
default values. It stays 1 until the reset interrupt status register is read and then becomes 0.
14
PKV
0
Indicates that an interrupt was caused when the selected voltage input is above the value in the
VPINTLVL register.
15
PKI
0
Indicates that an interrupt was caused when the selected current input is above the value in the
IPINTLVL register.
16
17
WFSM
REVPAP
0
0
Indicates that new data is present in the waveform register.
Indicates that an interrupt was caused by a sign change in the watt calculation among any one of the
phases specified by the TERMSEL bits in the COMPMODE register.
18
REVPRP
0
Indicates that an interrupt was caused by a sign change in the VAR calculation among any one of the
phases specified by the TERMSEL bits in the COMPMODE register.
19
SEQERR
0
Indicates that an interrupt was caused by a zero crossing from Phase A followed not by the zero
crossing of Phase C but by that of Phase B.
Rev. E | Page 69 of 72
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